School of Electronics Engineering (SENSE) is organizing a 5-Day Workshop on VLSI Device and Circuit Design Tools -Online Mode for Faculty/UG/PG/Research Scholars/ Industry Participants from 22nd June to 26th June 2021. This workshop is being organized by the SENSE in association with Academic Staff College, VIT-AP University, Near Vijayawada(AP).
This workshop will focus on the following topics
- Introduction to Non-Classical MOS Transistor
- Live demonstration of device simulation and analysis using Synopsys Sentaurus 3D TCAD tool
- Physical Insights into the nature of Gate-induced Drain Leakage in Emerging Nano-scale FETs
- ASIC and full-custom design flow using Synopsys tool
- BACK-END design flow, generation of GDS-II, and use of Fin-FET library in Cadence
- Static timing analysis using Tempus and clock tree synthesis concept in Cadence
- Demonstration of full-custom design using Tanner EDA and Mentor tool
- Xilinx FPGA design flow
- Demonstration on system generator flow with Matlab
- Demonstration on PYNQ platform with Vivado
- Introduction to HDL Verification and UVM
- Learn to build UVM testbench from scratch
The last date for registration is 18-06-2021(Friday) – (IST) 5:00 PM
Limited seats 60 only, first-come-first-serve basis
Registration Fee: ₹500 / $6.87
Registration Form and Payment Link – Register through the link given below. The payment link is available inside the registration form. Pay the registration fee and upload the proof in the appropriate place.
https://forms.gle/SErtxdvFhfyvXJZB8
For further details download the brochure
Please feel free to contact:
Coordinators:
Dr. Rohit Lorenzo (email: rohit.lorenzo@vitap.ac.in), Contact No: 7983315021
Dr. Chandan Kumar Pandey (email: chandan.pandey@vitap.ac.in), Contact No: 9040206739
Dr. Umakanta Nanda (email: umakanta.n@vitap.ac.in), Contact No: 9437746198
Co-coordinators:
Dr. Nalluri Purnachand (email: purnachand.n@vitap.ac.in), Contact No: 9182410617
Dr. Telajala Venkata Mahendra(email: mahendra.t@vitap.ac.in), Contact No: 8985843575
